EDN

Introduction to and Regression Test for OCP SystemC Channel Models

As the VLSI process technology continuously advances, the System-on-Chip (SoC) design methodology has become a main design trend for semiconductor products. A single ...
EDN

SystemC ‘primer’ explains language basics

ALLENTOWN, Pa. — Noted EDA author J. Bhasker, architect at eSilicon, has turned his attention toward SystemC in his latest book, A SystemC Primer. The textbook provides an overview of the language and ...
Electronic Design

System Verification Comes To SystemC

It is widely accepted that system verification is the most imposing obstacle to meeting time-to-market schedules. Now, the verification process has become even more time-consuming and expensive. These ...
Design-Reuse

From Behavioral to RTL Design Flow in SystemC

This paper reports the scientific collaboration between LLR and PROSILOG. The aim of this collaboration was to show the possibility to quickly implement a system into a FPGA, using SystemC 4 as the ...
Electronic Design

Full-Chip High-Level Synthesis Tool Adds SystemC Support

High-level synthesis (HLS) continues to grow in favor among beleaguered system-on-a-chip (SoC) design teams. At the same time, EDA vendors continue to increase the capabilities of their tools. The ...