EDN

DFT Analyzer Validates Design-For-Test Features

Asset InterTech has announced its DFT Analyzer, which according to the company reduces manufacturing and test costs by validating the boundary-scan design-for-test features in a circuit-board design ...
EDN

Moving DFT into chip design with hardware emulation

Of all the electronic design automation (EDA) tools on the market, design for test (DFT) may be the most under-appreciated; even though building testability into a chip during the design phase will ...
Electronic Design

A Methodology to Speed DFT Signoff

Shipping high-quality ICs requires that design-for-test (DFT) methodologies be included in a design. DFT provides external access at the device’s I/O pins to internal registers to either control or ...
Electronic Design

Twin DFT and Mission-Critical Safety Apps for Pre-Silicon Design Verification

The design-for-test (DFT) technology was driven by the need to harness the runaway cost of testing silicon chips on the manufacturing floor. This phenomenon eventually became close to 40% of the cost ...
Semiconductor Engineering

Smart DFT Infrastructure And Automation Are Key To Managing Design Scaling

This paper describes how using a smarter DFT infrastructure and automation can greatly improve the DFT schedule. A structural DFT infrastructure based on plug-and-play principles is used to enable ...
Semiconductor Engineering

Smarter DFT Infrastructure And Automation Emerge As Keys To Managing DFT Design Scaling

The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, ...
Digi Times

Mediatek adopts SpyGlass DFT solution

Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, announced that MediaTek has adopted Atrenta's SpyGlass DFT (Design for Test) ...